1. Field of the Invention
The present invention relates to a method for packaging a semiconductor device having projected electrodes, in which metallic projections are formed on the electrodes.
2. Description of the Related Art
In recent years, a tape-automated bonding (TAB) method and a flip chip method have been practically used for packaging a semiconductor device (semiconductor chip) with a greater number of pins at narrower pitches. These methods require forming bumps (metallic projections) on electrodes of the semiconductor chip for bonding the semiconductor chip to a wiring board. Forming bumps, therefore, has become one of the critical technologies in the field of LSI packaging. Generally, bumps are formed by plating at a stage of the wafer process. This method, however, requires additional apparatuses for evaporation, etching, and the like at subsequent steps, causing high cost. There is another known method which includes forming bumps on a separate substrate (bump substrate) and transferring the bumps onto electrodes of a semiconductor chip from the bump substrate.
U.S. Pat. No. 3,621,564 discloses a method for forming bumps made of solder on a bump substrate and transferring them onto electrodes of a semiconductor chip. This method, however, has a problem as follows: when the semiconductor chip having such bumps made of solder is bonded to a wiring board by mutual diffusion, stress tends to be produced in the bumps as temperature rises due to the difference of expansion coefficients between the semiconductor chip and the wiring board. This causes a decrease in reliability of any resultant product. To solve this problem and to keep high reliability, there has been developed a method for bonding the semiconductor chip to the wiring board by contact, not by diffusion. According to this method, material for bumps should be chemically stable and resistive to the formation of an oxide film on the surface. At present, Au is mainly used as such material.
A conventional method for forming bumps on a semiconductor chip by transfer and packaging such a semiconductor chip with the bumps will be described.
FIGS. 7A to 7D schematically show steps for a conventional method for packaging a semiconductor device having projected electrodes on a board. In this method, a chip tray is provided for transporting LSI chips with bumps formed .thereon.
FIG. 7A shows a first placement step, where electrodes 7 of an LSI chip 9 and bumps 5 made of Au on a bump substrate 4 are aligned with each other so as to place the LSI chip 9 in position on the bump substrate 4. The bump substrate 4 includes a conductive film 2 made of ITO or the like formed on one side of an insulating base i made of glass or the like. The bumps S are formed on the conductive film 2 of the bump substrate 4 by electroplating using a photoresist as a mask. The LSI chip 9 is lowered with the support of a vacuum collet 6 and placed on the bump substrate 4 so that the electrodes 7 of the LSI chip 9 and the bumps 5 on the bump substrate 4 are matched with each other.
FIG. 7B shows a first bonding step, where the LSI chip 9 is pressed and heated by means of a pressure tool 8, so that the electrodes 7 of the LSI chip 9 and the bumps 5 on the bump substrate 4 are bonded with each other by forming an alloy thereof for transferring the bumps 5 to the electrodes 7. FIG. 8 shows a sectional view of the bump substrate 4 and the LSI chip 9 at this bonding step. At this time, the bonding strength of the bumps 5 with the electrodes 7 is made greater than that of the bumps 5 with the bump substrate 4. The word "bonding" as used herein has a comparatively broader meaning, including the case where two kinds of metal are joined together without being alloyed.
FIG. 7C shows a transfer step and a holding step. In the transfer step, the LSI chip 9 is lifted up by sucking it with the vacuum collet 6 from the bump substrate 4. By this sucking, %he bumps 5 are removed from the bump substrate 4 and transferred to the electrodes 7 of the LSI chip 9. Then, in the holding step, the LSI chip 9 with the electrodes 7 carrying the bumps 5 is moved to a chip tray 12 so as to be held in a pocket 13 of the chip tray 12.
The above-described steps, i.e., the first placement step (FIG. 7A), the first bonding step (FIG. 7B), and the transfer step and the holding steps (FIG. 7C) are repeated for each LSI chip 9 until a plurality of LSI chips 9 with the bumps 5 transferred thereto are held on the chip tray 12. The chip tray 12 with the plurality of LSI chips 9 held thereon is then transported to a subsequent step.
FIG. 7D shows a sucking step, a second placement step, and a second bonding step. The chip tray 12 holding the LSI chips 9 thereon is transported and placed on an X-Y table 14. In the sucking step, each of the LSI chips 9 with the bumps 5 is lifted up from the pocket 13 of the chip tray 12 by sucking with a vacuum collet 11. In the second placement step, the LSI chip 9 is placed on lead wirings 16 patterned on a wiring board 15 so that the bumps 5 on the LSI chip 9 can be connected to the lead wirings 16 on the wiring board 15. Then, in the second bonding step, the LSI chip 9 is bonded with the wiring board 15.
FIGS. 9A to 9C show steps for fabricating the bump substrate 4 with the bumps 5.
Referring to FIG. 9A, the conductive film 2 is formed on the insulating base 1. An insulating film 3 is then formed on the conductive film 2, and openings 17 are formed at positions corresponding to the positions of electrodes of a semiconductor chip to which bumps are to be transferred. The insulating base 1 is made of glass or quartz, the conductive film 2 of Ti/Pt or ITO, and a resist is used as the insulating film 3. Typically, the conductive film 2 and the insulating film 3 respectively have a thickness of approximately 1 .mu.m, the openings 17 have a diameter of approximately 10-30 .mu.m, and the distance between the adjacent openings 17 is approximately 20 .mu.m.
Then, referring to FIG. 9B, the bumps 5 are formed at the openings 17 by electroplating using the conductive film 2 as one of an electrode pair. At this time, the bumps 5 are formed so as to be provided with inner stress by controlling the current density and temperature at the electroplating. This is done so as to reduce the bonding strength of the bumps 5 with the bump substrate 4 to be smaller than the bonding strength of the bumps 5 with the electrodes 7 of the LSI chip 9, thereby to effect the transfer of the bumps on the bump substrate 4 to the electrodes 7 of the LSI chip 9 at the aforementioned first bonding step (refer to FIG. 7B).
The insulating film 3 is then removed as shown in FIG. 9C, thus obtaining the bump substrate 4 having the bumps 5 thereon.
FIGS. 10A and 10B show sectional views of the LSI chip 9 with the bumps 5 transferred thereto, and the wiring board 15 at the second bonding step. FIG. 10A shows a method for bonding the LSI chip 9 with the wiring board 15 by applying a photo-cure resin 18 therebetween. In this method, the bumps 5 of the LSI chip 9 and the lead wirings 16 are pressed to each other by the contraction produced when the photo-cure resin 18 is cured. In this case, an alloy layer is not formed between the bumps 5 and the lead wirings 16.
FIG. 10B shows another method for bonding the LSI chip 9 with the wiring board 15. In this method, the bumps 5 and the lead wirings 16 are bonded by thermocompression. In this case, a thin alloy layer is formed between the bumps 5 and the lead wirings 16. Other methods such as the TAB method can also be used for bonding the LSI chip 9 with the wiring board 15.
In the above-described conventional methods for packaging a semiconductor device having projected electrodes, it is required to align each LSI chip 9 with the wiring board 15, before the second alignment step, by correcting a displacement of the electrodes 7 of the LSI chip 9 with regard to the lead wirings 16 of the wiring board 15 through image recognition. FIG. 11 shows this displacement correcting step and the subsequent second placement step.
Referring to FIG. 11, the LSI chip 9 held in the pocket 13 of the chip tray 12 placed on the X-Y table 14 is lifted up by sucking with the vacuum collet 11 and transported to the wiring board 15 placed on another X-Y table 19. Because the LSI chip 9 may be shifted inside the pocket 13 of the chip tray 12 during 25 the transportation, positioning between the transported LSI chap 9 and the wiring board 15 to be bonded with the LSI chip 9 may nor be accurate, but a displacement L of the LSI chip 9 from an intended position on the wiring board 15 may be produced. In order to correct the displacement L, an alignment camera 20 is disposed between the LSI chip 9 and the wiring board 15 to monitor the positions thereof. After the displacement L has been corrected based on the results of the image recognition, the LSI chip 9 is placed on the wiring board 15.
The above displacement correction using the alignment camera 20 is performed for each LSI chip 9 when it is transported to the wiring board 15, as shown in FIG. 11, because each LSI chip 9 can be individually shifted inside the pocket 13 of the chip tray 12 during the transportation of the chip tray 12. This displacement correcting step requires two to ten seconds per LSI chip, indicating that in total a considerable time is required for this step.
Other problems are that dust may attach to 15 the bumps 5 when the LSI chip 9 is moved to the chip tray 12 and that, because the LSI chip 9 held on the chip tray 12 may be shifted inside the pocket 13 of the chip tray 12 due to vibration or the like during the transportation of the chip tray 12, stress may be produced in particular bumps 5, causing deformation of the bumps 5.
FIGS. 12A and 12B show the LSI chip 9 bonded to the wiring board 15, in which one of the bumps 5 has dust 21 attached thereto (FIG. 12A) or is deformed (FIG. 12B). As is seen from these figures, when the LSI chip 9 having such contaminated or deformed bumps 5 is bonded to the wiring board 15, inferior connection or disconnection may be caused.